1. Field of the Invention
Embodiments of the present invention generally relate to a hardware emulator and, more specifically, a hardware emulation unit having a shadow processor.
2. Description of the Related Art
Hardware emulators are programmable devices used in the verification of hardware designs. A common method of hardware design verification uses processor-based hardware emulators to emulate the design. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
A hardware emulator generally comprises a computer workstation for providing emulation support facilities, i.e., emulation software, a compiler, and a graphical user interface to allow a person to program the emulator, and an emulation engine for performing the emulation. The emulation engine is comprised of at least one emulation board, and each emulation board contains individual emulation circuits. Each individual emulation circuit contains multiple emulation processors, and each emulation processor is capable of mimicking a logic gate in each emulation step. Thus, the hierarchy of the emulation engine is an emulation board, multiple emulation integrated circuits, and multiple processors that are part of each emulation integrated circuit.
Each processor is connected to a data array. The data array is a special memory that has multiple read ports and supplies input data to the processor via each read port. The processor evaluates the data supplied from the data array in accordance with an instruction word supplied from an instruction memory. The processor does not always require input data from all of the read ports of the data array. For example, if a data array has four read ports, and a processor is evaluating a function that requires two operands, input data supplied from two out of the four read ports of the data array will be unused by the processor.
The bandwidth of the processor can be calculated by the equation F×N bits/second, where F is the processor clock frequency and N is the number of read ports on the data array that supply input data to the processor. On a four-read port data array, statistically only 2.5 read ports are accessed by the processor during an emulation step. It is well known that processor bandwidth is a significant limiting factor of hardware emulator performance.
Thus, there is a need in the art for a hardware emulator having improved utilization of the available processor bandwidth.